Generally speaking, computer systems typically include one or more central processor units (CPUs). In order to reduce power consumption and increase the performance of those CPUs, selected signals are operated in a xe2x80x9clow voltage swingxe2x80x9d manner. Low voltage swing signals typically represent digital data with a representative voltage that is less than the supply voltage (Vdd) level. Low swing voltage signals are typically generated in true/complement pairs, referred to as xe2x80x9cdifferentialxe2x80x9d pairs. The prior art sense amplifiers operate by sensing the voltage differential between the true/complement pair to determine the logic level of the signal.
For example, the circuitry of a CPU may be powered by a Vdd supply voltage of 2.0 Volts. An associated pair of low voltage swing signals may develop a voltage differential of only +0.2 Volts to represent logic high data and xe2x88x920.2 Volts to represent logic low data. Such low voltage swing signals can increase performance because the amount of time to generate a voltage differential of 0.8 Volts is significantly shorter than to transition that signal from 2.0 to 0 Volts. A signal that transitions from 2.0 to 0 Volts (i.e., from Vdd to Vss) is referred to as a xe2x80x9crail-to-railxe2x80x9d signal.
While low voltage swing signals present benefits to a CPU, they also add additional design requirements. For example, CPUs that employ low voltage swing signals, such as to represent data read from hardware registers, typically include amplifiers referred to as xe2x80x9csense amplifiersxe2x80x9d for detecting the logic levels of those low voltage swing signals. When such a register is accessed, data that is stored therein is presented to the sense amplifier. That sense amplifier is designed to detect the logic levels of the low swing voltage signals and convert them to rail-to-rail voltage signals. Those rail-to-rail voltage signals can be input to other circuits that operate on the data, for example the CPU""s floating point data store unit.
Such sense amplifiers are replicated many times in a typical CPU. Accordingly, the size of each device is critical to the total area used by such a CPU. Further, the chip real estate that each sense amplifier consumes reduces the total area available for other devices.
In the past, sense amplifiers have included at least two input stages connected to a corresponding number of data lines. Those input stages are connected to each signal of a true/complement or differential pair. The differential pairs are conveyed by wires across relatively large distances from the sourcing location to the destination location, e.g. the sense amplifier. Accordingly, those wires must be physically wide enough to present as little resistance as possible to the low swing voltage signals, such that the voltage levels are not degraded. Because those wires are connected to the inputs of each sense amplifier, they significantly increase the amount of real estate that is used by the floating point unit.
Prior art approaches to reducing the area of such sense amplifiers have used a reference voltage supply circuit. The reference voltage supply circuit is used as a reference to determine the logic level of an associated low voltage swing signal. Such an approach poses area, power consumption, process tracking and electrical noise concerns.
Generally, the sense amplifier of the present invention senses the logic level of data that is conveyed using a low voltage swing signal. The data is input to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation. Rather, it uses the same voltage supply that is used to power the rest of the circuit. Accordingly, the area used by the sense amplifier is significantly reduced.
More specifically, a method is provided for sensing an input voltage level of a data signal. Such a method involves pre-charging, and subsequently discharging, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a chip voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance (i.e., conductance capacity), it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharges is the fastest and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated.
With such a structure, the data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized power supply for proper operation. Rather it uses the same power supply that is used to power the rest of the circuit. Accordingly, the area used by the sense amplifier is significantly reduced.
In a further aspect of the present invention, the discharge operation associated with one of the nodes, that is discharging at a faster rate, is allowed to continue while the discharge operation associated with the other node is terminated. Accordingly, the method allows the sensing operation to operate using a single data signal. Therefore, the semiconductor area that is used to practice the sensing operation is significantly reduced.
The input data signal may be a single low voltage swing signal. The sense amplifier may also include a pull-up unit coupled to the internal signal nodes for pulling the node that is discharged at a slower rate to a high logic level.
Further, the sense amplifier may include an evaluate unit, such as a transistor, connected to an electrical ground and to the pair of discharge paths for conveying the charge to electrical ground, and for initiating that conveyance when the input data signal achieves a voltage level that is capable of being resolved by the sense amplifier.
Further still, one of the discharge paths may include a pair of transistors connected in series by one of the internal signal nodes. That structure is connected in parallel with another, similar series connection of transistors. The input data signal is connected thereto.